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DS26503DK
Register Name: LEVEL2
Register Description: DS26503 Pin Settings (RMODE3, RMODE2, RMODE1, RMODE0)
Register Offset: 0x0012
Bit #
Name
Default
7
RMODE3
tri
0
6
RMODE3
_Lev
0
5
RMODE2
tri
0
4
RMODE2
_Lev
0
3
RMODE1
tri
0
2
RMODE1
_Lev
0
1
RMODE0
tri
0
0
RMODE0
_Lev
0
Note: This register is only valid in hardware mode (BIS[1:0] = 11), and is ignored for other modes.
Bits 7 and 6: DS26503 RMODE3 Tri-State and Level (RMODE3tri and RMODE3_Lev)
00 = FPGA drives RMODE3 with 0V
01 = FPGA drives RMODE3 with 3.3V
1x = FPGA tri-states RMODE3 pin
Bits 5 and 4: DS26503 RMODE2 Tri-State and Level (RMODE2tri and RMODE2_Lev)
00 = FPGA drives RMODE2 with 0V
01 = FPGA drives RMODE2 with 3.3V
1x = FPGA tri-states RMODE2 pin
Bits 3 and 2: DS26503 RMODE1 Tri-State and Level (RMODE1tri and RMODE1_Lev)
00 = FPGA drives RMODE1 with 0V
01 = FPGA drives RMODE1 with 3.3V
1x = FPGA tri-states RMODE1 pin
Bits 1 and 0: DS26503 RMODE0 Tri-State and Level (RMODE0tri and RMODE0_Lev)
00 = FPGA drives RMODE0 with 0V
01 = FPGA drives RMODE0 with 3.3V
1x = FPGA tri-states RMODE0 pin
Register Name: LEVEL3
Register Description: DS26503 Pin Settings (RSM, RITD)
Register Offset: 0x0013
Bit #
Name
Default
7
—
0
6
—
0
5
RSMtri
0
4
RSM _Lev
0
3
—
0
2
—
0
1
RITDtri
0
0
RITD_Lev
0
Note: This register is only valid in hardware mode (BIS[1:0] = 11), and is ignored for other modes.
Bits 5 and 4: DS26503 RSM Tri-State and Level (RSMtri and RSM _Lev)
00 = FPGA drives RSM with 0V
01 = FPGA drives RSM with 3.3V
1x = FPGA tri-states RSM pin
Bits 1 and 0: DS26503 RITD Tri-State and Level (RITDtri and RITD_Lev)
00 = FPGA drives RITD with 0V
01 = FPGA drives RITD with 3.3V
1x = FPGA Tristates RITD pin
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